This invention relates generally to semiconductor device package assembly, and in particular to semiconductor die flip chip package assembly. More specifically, the invention relates to an innovative material approach to lower stress and warpage in a laminate flip chip ball grid array (BGA).
In semiconductor device package assembly, a semiconductor die (also referred to as an integrated circuit (IC) chip or “chip”) may be bonded directly to a packaging substrate. Such die is formed with bumps of solder affixed to its I/O bonding pads. During packaging, the die is “flipped” onto its front surface (e.g., active circuit surface) so that the solder bumps form electrical and mechanical connections directly between the die and conductive metal pads on the packaging substrate. Underfill is generally applied between the gap formed by the solder bumps in order to further secure the die to the packaging substrate. A heat spreader is then attached over the die and packaging substrate. A semiconductor device package of this type is commonly called a “semiconductor die flip chip package.”
A problem with such a semiconductor die flip chip package is that it is subject to different temperatures during the packaging process. For instance, different temperatures arise with the cool down from the solder joining temperature and the underfill curing temperature. As a result, the package is highly stressed due to the different coefficients of thermal expansion (CTE) of the various package and die materials.
The high stress experienced by bonded materials during cooling may cause them to warp or crack and cause the package structure to bow. This problem is exacerbated in the case of a relatively large die, for example one 400 mm2 or larger, which has a relatively low CTE, attached to an organic substrate, which has a relatively high CTE. In addition, this problem is exacerbated in the case of a relatively thick die processed from a larger diameter wafer, for example a 300 mm diameter wafer. In some cases, the bow of the package will exceed the co-planarity specification for the semiconductor die flip chip package. With the advent of low-K dice, the high stress caused by the different CTE is even more of a concern. Low-K dielectric material layers in the low-K die are relatively brittle, rendering the low-K die susceptible to failure at even lower stress levels than conventional dice with FSG or USG dielectrics.
Accordingly, what is needed are semiconductor die flip chip packages and packaging methods that control package warpage (e.g., co-planarity) within acceptable limits for incorporation into electronic devices and that redistribute/absorb the package's internal stresses to enhance the reliability of the semiconductor die flip chip package.